Overview of Assertion-Based Verification and its Applications

Functional verification is a critical and timeconsuming task in complex VLSI designs. There are two main challenges to functional verification: the first is to insure that the input stimulus can control the function spots inside the design and the second is to insure that the errors can be observed at the design output(s). Over the years, assertion-based verification techniques have been playing a more important role as part of functional verification methodologies. In this paper, we provide an overview of concepts, benefits, languages, and applications of assertionbased verification. Keywords—Design verification, assertion-based verification, assertion languages.